The invention relates to a method used in Translation Pad Flip Chip (TPFC) IC substrate manufacturing process, and more particularly to a method used in manufacturing micro bump pitch IC substrates.
Recent product developments within the electronic industry are able to integrate more functions in a single substrate, which has led to a rapid increase in the number of I/Os used in a substrate, and a higher demand on packaging technology. With the Flip Chip (FC) technology currently used in the high level products, a higher packaging density is achieved, for example, the bump pitch between IC bumps can be reduced from 300 um to 200 um with the improvement of the alignment precision during the manufacturing process. However, with the next generation products that demand a packaging technology to reduce the bump pitch below 150 um, the conventional substrate structure and manufacturing methods can no longer meet such a demand. Therefore, the development of new substrate structure and manufacturing methods is imperative.
The conventional structure of IC substrates is a 4 to 10 layers of multi-layer printed circuit board, which is made of ceramics or organic materials. The conductive circuits between the layers are micro vias, mechanical or laser drilled, and wired to form bump pads for connecting IC bumps. Solder resist is used to define bump pad lands, and solders are applied by stencil printing. Conventionally, there are two ways to define the bump pad lands. The first is use solder resist to define the lands, as shown in FIG. 1, and the other is called metal defined lands, as shown in FIG. 2. When the bump pitch between IC bumps is reduced to below 150 um, the line between the bump pads will decrease the area of bump pad lands, which may cause solder paste unable to enter and fill solder mask opening where the grain size of the solder 102 is too large to be applied into the bump pad 101. This is problematic as the bonding strength is not sufficient to hold the IC chips, due to the lack of sufficient solder applied, as shown in FIG. 1. On the other hand, when when the solder resist 201, 202 covers less than 75 um in width, the solder resist 202 usually will not stick and is prone to peel off, as shown in FIG. 2. Hence, conventional methods are unable to manufacture micro bump pitch substrates.
The present invention provides a method to improve micro bump pitch IC substrates manufacturing process. It uses a dielectric layer to replace the conventional solder resist, then uses CCD high precision alignment laser drill to open up the defined bump pad lands, fills them with via plating filled metal accompanied by etching to enlarge the bump pads, and finally surface finishing the bump pads with various materials, such as solder, Ni/Au, or organic coating. This can simultaneously solve the problems of insufficient strength of bump pads, limitation of printing technology and being unable to apply the solder in the conventional technologies. Furthermore, the present invention can also translate the bump pads, passive component pads (e.g., capacitor pads), fiducial marks to the surface level, and avoid burying the pads in the solder resist that occurs in the conventional methods. The substrate structure also improves the underfilling step following the IC connection in the packaging process, and solves the micro bump pitch IC packaging problem. The present invention applies small bump pad at original design bump layer, and provides more circuit routability and higher packaging density. Further more, it can reduce layer count, get higher yield rate, and provide a total solution to the next generation high density IC design.
The present invention will become more obvious from the following description when taken in connection with the accompanying drawings which show, for purposes of illustration only, a preferred embodiment in accordance with the present invention.